The abstraction gap between theoretical Boolean logic and physical circuit implementation remains a persistent pedagogical challenge in Computer Architecture education. This paper investigates a simulation-first workflow that uses Tinkercad Circuits as a cloud-based digital model environment for pre-physical verification of hardware logic designs. The proposed workflow follows a four-phase iterative process: logic design specification, virtual prototyping, virtual verification with integrated debugging tools, and physical breadboard implementation. A pilot implementation with 20 first-year computer engineering students showed promising descriptive outcomes: 18 students, or 90%, completed all assignments with correct functionality; average laboratory time decreased from 120 minutes to 80-90 minutes per assignment; and instructor assistance shifted from mechanical troubleshooting to conceptual analysis of logic behavior, timing, and design alternatives. Because the study involved a single cohort without a parallel control group, these findings should be interpreted as preliminary evidence of feasibility and pedagogical potential rather than statistically conclusive proof of superiority over breadboard-first instruction.